Title page for E-project-101507-105824

Project Type MQP

Submission date 2007-10-15

Author
Abhilash Nair, ECE

URN E-project-101507-105824

Title Design of a 16-bit 10Mhz Pipeline ADC using the SPLIT-ADC architecture in 0.25u CMOS

Advisor
McNeill, John A, EE

Availability unrestricted

Abstract
This paper discusses the design of a 16-bit 10MHz pipeline Analog to Digital Converter (ADC) using the "Split ADC architecture". A system and circuit level design of each component of the ADC was created in Cadence. Features of the ADC were simulated in Matlab to test and examine its basic functionality. Transient analysis of the system level design was conducted to verify the performance of the ADC. Methods to correct non-linearities were identified and investigated.

Files
ISCAS_paper_02.05.pdf
MQP_Report_10_14_07.pdf

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Project Type	MQP
Submission date	2007-10-15
Author	Abhilash Nair, ECE
URN	E-project-101507-105824
Title	Design of a 16-bit 10Mhz Pipeline ADC using the SPLIT-ADC architecture in 0.25u CMOS
Advisor	McNeill, John A, EE
Availability	unrestricted
Abstract This paper discusses the design of a 16-bit 10MHz pipeline Analog to Digital Converter (ADC) using the "Split ADC architecture". A system and circuit level design of each component of the ADC was created in Cadence. Features of the ADC were simulated in Matlab to test and examine its basic functionality. Transient analysis of the system level design was conducted to verify the performance of the ADC. Methods to correct non-linearities were identified and investigated.
Files	ISCAS_paper_02.05.pdf MQP_Report_10_14_07.pdf