Worcester Polytechnic Institute Electronic Theses and Dissertations Collection

Title page for ETD etd-011410-142841

Document Typethesis
Author NameShen, Chen
TitleDesign and Implementation of
DepartmentElectrical & Computer Engineering
  • Xinming Huang, Advisor
  • Berk Sunar, Committee Member
  • Andrew G. Klein, Committee Member
  • Keywords
  • soft-output decoding
  • FPGA
  • sphere detection
  • MIMO
  • Date of Presentation/Defense2009-12-21
    Availability unrestricted


    Multiple-input multiple-output (MIMO) technique in communication system has been widely researched. Compared with single-input single-output (SISO) communication, its properties of higher throughput, more ecient spectrum and usage make it one of the most significant technology in modern wireless communications. In MIMO system, sphere detection is the fundamental part. The purpose of traditional sphere detection is to achieve the maximum likelihood (ML) demodulation of the MIMO system. However, with the development of advanced forward error correction (FEC) techniques, such as the Convolutional code, Turbo code and LDPC code, the sphere detection algorithms that can provide soft information for the outer decoder attract more interests recently. Considering the computing complexity of generating the soft information, it is important to develop a high-speed VLSI architecture for MIMO detection.

    The first part of this thesis is about MIMO sphere detection algorithms. Two sphere detection algorithms are introduced. The depth first Schnorr-Euchner (SE) algorithm which generates the ML detection solution and the width first K-BEST algorithm which only generates the nearly-ML detection solution but more efficient in implementation are presented. Based on these algorithms, an improved nearly-ML algorithm with lower complexity and limited performance lose, compared with traditional K-BEST algorithms, is presented. The second part is focused on the hardware design. A 4*4 16-QAM MIMO detection system which can generate both soft information and hard decision solution is designed and implemented in FPGA. With the fully pipelined and parallel structure, it can achieve a throughput of 3.7 Gbps. In this part, the improved nearly-ML algorithm is implmented as a detector to generat both the hard output and candidate list. Then, a soft information calculation block is designed to succeed the detector and produce the log-likelihood ratio (LLR) values for every bit as the soft output.

  • thesis.pdf

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