Worcester Polytechnic Institute Electronic Theses and Dissertations Collection

Title page for ETD etd-042710-152438


Document Typedissertation
Author NameDavid, Christopher Leonidas
URNetd-042710-152438
Title All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters
DegreePhD
DepartmentElectrical & Computer Engineering
Advisors
  • John A. McNeill, Advisor
  • Donald R. Brown, Committee Chair
  • Michael Coln, Committee Chair
  • Keywords
  • Successive
  • Approximation
  • Digital
  • Background
  • Calibration
  • ADC
  • Analog-to-Digital
  • SAR
  • Time-Interleaved
  • Converter
  • Date of Presentation/Defense2010-04-13
    Availability unrestricted

    Abstract

    The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures.

    The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples.

    The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.

    Files
  • splinta_splitsar_thesis_final.pdf

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