Title page for ETD etd-042810-191950

Document Type thesis

Author Name Brenneman, Cody R.

URN etd-042810-191950

Title Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter

Degree MS

Department Electrical & Computer Engineering

Advisors
John McNeill, Advisor
Stephen Bitar, Committee Member
Andrew Klein, Committee Member

Keywords
ADC
Circuit design
Calibration
SAR

Date of Presentation/Defense 2010-04-27

Availability unrestricted

Abstract
As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits.

The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm². The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.

Files
brenneman.pdf

Browse by Author | Browse by Department | Search all available ETDs

Questions? Email etd-questions@wpi.edu
Maintained by webmaster@wpi.edu

Document Type	thesis
Author Name	Brenneman, Cody R.
URN	etd-042810-191950
Title	Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter
Degree	MS
Department	Electrical & Computer Engineering
Advisors	John McNeill, Advisor Stephen Bitar, Committee Member Andrew Klein, Committee Member
Keywords	ADC Circuit design Calibration SAR
Date of Presentation/Defense	2010-04-27
Availability	unrestricted
Abstract As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm². The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
Files	brenneman.pdf