Title page for ETD etd-0504101-114017

Document Type thesis

Author Name Wollinger, Thomas Josef

Email Address wollinger at fulbrightweb.org

URN etd-0504101-114017

Title Computer Architectures for Cryptosystems Based on Hyperelliptic Curves

Degree MS

Department Electrical & Computer Engineering

Advisors
Prof. Christof Paar, Advisor
Prof. Berk Sunar, Committee Member
Prof. William J. Martin, Committee Member

Keywords
binary field arithmetic
gcd
hardware architectures
polynomial arithmetic
cryptosystem
Hyperelliptic curves

Date of Presentation/Defense 2001-05-01

Availability unrestricted

Abstract
Security issues play an important role in almost all modern communication and
computer networks. As Internet applications continue to grow
dramatically, security requirements have to be
strengthened. Hyperelliptic curve cryptosystems (HECC) allow for
shorter operands at the same level of security than other public-key
cryptosystems, such as RSA or Diffie-Hellman. These shorter operands
appear promising for many applications.

Hyperelliptic curves are a generalization of elliptic curves and they
can also be used for building discrete logarithm public-key schemes. A
major part of this work is the development of computer architectures
for the different algorithms needed for HECC. The architectures are
developed for a reconfigurable platform based on Field Programmable
Gate Arrays (FPGAs). FPGAs combine the flexibility of software
solutions with the security of traditional hardware
implementations. In particular, it is possible to easily change all
algorithm parameters such as curve coefficients and underlying finite
field.

In this work we first summarized the theoretical background of
hyperelliptic curve cryptosystems. In order to realize the operation
addition and doubling on the Jacobian, we developed architectures for
the composition and reduction step. These in turn are based on
architectures for arithmetic in the underlying field and for
arithmetic in the polynomial ring. The architectures are described in
VHDL (VHSIC Hardware Description Language) and the code was
functionally verified. Some of the arithmetic modules were also
synthesized. We provide estimates for the clock cycle count for a
group operation in the Jacobian. The system targeted was HECC of genus
four over GF(2^41).

Files
wollinger.pdf

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Document Type	thesis
Author Name	Wollinger, Thomas Josef
Email Address	wollinger at fulbrightweb.org
URN	etd-0504101-114017
Title	Computer Architectures for Cryptosystems Based on Hyperelliptic Curves
Degree	MS
Department	Electrical & Computer Engineering
Advisors	Prof. Christof Paar, Advisor Prof. Berk Sunar, Committee Member Prof. William J. Martin, Committee Member
Keywords	binary field arithmetic gcd hardware architectures polynomial arithmetic cryptosystem Hyperelliptic curves
Date of Presentation/Defense	2001-05-01
Availability	unrestricted
Abstract Security issues play an important role in almost all modern communication and computer networks. As Internet applications continue to grow dramatically, security requirements have to be strengthened. Hyperelliptic curve cryptosystems (HECC) allow for shorter operands at the same level of security than other public-key cryptosystems, such as RSA or Diffie-Hellman. These shorter operands appear promising for many applications. Hyperelliptic curves are a generalization of elliptic curves and they can also be used for building discrete logarithm public-key schemes. A major part of this work is the development of computer architectures for the different algorithms needed for HECC. The architectures are developed for a reconfigurable platform based on Field Programmable Gate Arrays (FPGAs). FPGAs combine the flexibility of software solutions with the security of traditional hardware implementations. In particular, it is possible to easily change all algorithm parameters such as curve coefficients and underlying finite field. In this work we first summarized the theoretical background of hyperelliptic curve cryptosystems. In order to realize the operation addition and doubling on the Jacobian, we developed architectures for the composition and reduction step. These in turn are based on architectures for arithmetic in the underlying field and for arithmetic in the polynomial ring. The architectures are described in VHDL (VHSIC Hardware Description Language) and the code was functionally verified. Some of the arithmetic modules were also synthesized. We provide estimates for the clock cycle count for a group operation in the Jacobian. The system targeted was HECC of genus four over GF(2^41).
Files	wollinger.pdf