Worcester Polytechnic Institute Electronic Theses and Dissertations Collection

Title page for ETD etd-090399-090413


Document Typethesis
Author NameBlum, Thomas
Email Address tblum at crcg.edu
URNetd-090399-090413
TitleModular Exponentiation on Reconfigurable Hardware
DegreeMS
DepartmentElectrical & Computer Engineering
Advisors
  • Christof Paar, Advisor
  • Fred J. Looft, Committee Member
  • Yusuf Leblebici, Committee Member
  • Keywords
  • public-key cryptography
  • FPGA
  • Montgomery multiplication
  • Modular Exponentiation
  • RSA
  • Reconfigurable Hardware
  • Date of Presentation/Defense1999-04-08
    Availability unrestricted

    Abstract

    It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. A central tool for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions, this contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs). The proposed architectures perform modular exponentiation with very long integers. This operation is at the heart of many practical public-key algorithms such as RSA and discrete logarithm schemes. We combine two versions of Montgomery modular multiplication algorithm with new systolic array designs which are well suited for FPGA realizations. The first one is based on a radix of two and is capable of processing a variable number of bits per array cell leading to a low cost design. The second design uses a radix of sixteen, resulting in a speed-up of a factor three at the cost of more used resources. The designs are flexible, allowing any choice of operand and modulus. Unlike previous approaches, we systematically implement and compare several versions of our new architecture for different bit lengths. We provide absolute area and timing measures for each architecture on Xilinx XC4000 series FPGAs. As a first practical result we show that it is possible to implement modular exponentiation at secure bit lengths on a single commercially available FPGA. Secondly we present faster processing times than previously reported. The Diffie-Hellman key exchange scheme with a modulus of 1024 bits and an exponent of 160 bits is computed in 1.9 ms. Our fastest design computes a 1024 bit RSA decryption in 3.1 ms when the Chinese remainder theorem is applied. These times are more than ten times faster than any reported software implementation. They also outperform most of the hardware-implementations presented in technical literature.

    Files
  • blum.pdf

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