Document Type thesis Author Name Coyne, Jack W URN etd-090507-114502 Title FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography Degree MS Department Electrical & Computer Engineering Advisors R. James Duckworth, Advisor David Cyganski, Committee Member John Orr, Committee Member Keywords hardware accelerator SVD digital signal processing FPGA Date of Presentation/Defense 2007-08-31 Availability unrestricted
This thesis describes a co-processor system that has been designed to accelerate computations associated with Singular Value Array Reconciliation Tomography (SART), a method for locating a wide-band RF source which may be positioned within an indoor environment, where RF propagation characteristics make source localization very challenging. The co-processor system is based on field programmable gate array (FPGA) technology, which offers a low-cost alternative to customized integrated circuits, while still providing the high performance, low power, and small size associated with a custom integrated solution. The system has been developed in VHDL, and implemented on a Virtex-4 SX55 FPGA development platform. The system is easy to use, and may be accessed through a C program or MATLAB script. Compared to a Pentium 4 CPU running at 3 GHz, use of the co-processor system provides a speed-up of about 6 times for the current signal matrix size of 128-by-16. Greater speed-ups may be obtained by using multiple devices in parallel. The system is capable of computing the SART metric to an accuracy of about -145 dB with respect to its true value. This level of accuracy, which is shown to be better than that obtained using single precision floating point arithmetic, allows even relatively weak signals to make a meaningful contribution to the final SART solution.
Files jwcoyne_01_mastersthesis.pdf jwcoyne_02_thesiscover.pdf
Browse by Author | Browse by Department | Search all available ETDs
Questions? Email email@example.com