Prior to 2007

Reconfigurable Hardware and Cryptographic Algorithms

Adam Elbirt (student) & Christof Paar, WPI ECE Department
Tuesday, February 8, 2000
AK218 - 3:00 p.m.

Abstract

With the expiration of the Data EnCryption Standard (DES) in 1998, the Advanced EnCryption Standard (AES) development process by NIST is well underway. The technical analysis used in determining which of the potential AES candidates will be selected as the Advanced EnCryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of enCryption algorithms as they provide Cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions.

This talk provides a general introduction to Cryptographic schemes and their implementation in reconfigurable hardware. Then, significance of an FPGA implementation of Serpent, one of the Advanced EnCryption Standard candidate algorithms, is investigated. Multiple architecture options of the Serpent algorithm will be explored with a strong focus being placed on a high speed implementation within an FPGA in order to support security for current and future high bandwidth applications. One of the Main findings is that Serpent can be implemented with enCryption rates beyond 4 Gbit/s on current FPGAs.

February 8, 2000