Prior to 2007

Design-in-Reliability for Gigascale System-On-a-Chip (SOC) Integration

Sugn-Mo (Steve) Kang
Head, Department of Electrical and Computer Engineering
University of Illinois

Abstract

The monolithic integration of MOS transistors has been continued over the last few decades despite many challenges in technology development and design complexity. The earlier negative predictions for hitting the limit of integration have been broken with innovative solutions. The Moore's law that predicted doubling of the chip complexity for every two years has been held so far. Major bottlenecks to higher integration have been removed with the conviction that they can be removed not to violate the Moore's law. The technology roadmap indicates that gigascale system-on-a-chip (SOC) integration with ultra small feature sizes will become a reality in the near future. However, there exist increasing concerns for reliability of SOCs. Already many IC products suffer from ESD, electromigration and other reliability problems. As more and more microchips are used in almost every aspect of our life, such as in automobiles, airplanes, cellular phones, and laptops, the reliability must be built in despite the increasing complexity. It is no longer affordable to treat reliability assurance as a backend process in the IC product development since the iteration cost is prohibitively large. In this talk we will discuss some of the important design challenges for building-in reliability (DIR) in complex SOCs while meeting conventional performance specifications. In particular, we will discuss new methodologies and CAD tools for DIR that have been developed at the University of Illinois at Urbana-Champagn in collaboration with SRC member companies.

October 15, 1999