ECE Graduate Seminar Lecture by Ronak Shah and John Henri, Cadence Design Systems

Thursday, November 14, 2019
4:00 pm to 5:00 pm
Floor/Room #: 
AK 219

Title:

Electronic Design Automation in 2020

 

Abstract:

The Electronic Design Automation (EDA) industry provides methodologies and tools for developing next generation chips and electronic systems. Since 1988, Cadence Design Systems has been a key provider of System Verification, IC Packaging Design, and PCB Design software. This talk will go into Cadence as a company and cover who we are, what we do, and why you should care. A high-level description of the modern design process for integrated circuits will be described with some dives into particular areas.  Current industry trends will be discussed. Join Ronak Shah and John Henri of Cadence Design Systems to hear how EDA tools come to life, solve the design problems of today, and scale up for tomorrow.

 

Speakers:

Ronak Shah and John Henri

Cadence Design Systems

 

Bio for Ronak Shah

Ronak Shah graduated with a Masters in EE from Arizona State University (ASU) in Dec’17 . He now works in the role of a Technical Marketing Engineer II for the OrCAD & PSpice solutions @Cadence Design Systems, where he applies his technical skills in a marketing field. Ronak's responsibilities include the coordination and measurement of marketing programs which involves close collaboration with customers, eco-system partners and worldwide channel partners. He provides technical support and training, defines and characterizes new product capabilities necessary to meet user requirements, and manages the interface between the R&D team and Cadence's user base.

 

Bio for John Henri

John Henri graduated with a BS in ECE from WPI in 1996 and is a 20-year veteran of the EDA industry.  He is a Software Architect for the Hardware System Verification division working on mapping behavioral logic to emulation systems.  He specializes in mapping verification constructs, such as functional coverage, assertions and other design checkers to hardware to improve verification of large System On a Chip designs.  He is also a co-chair of Cadence's internal East Coast Technical Conference.

 

Host: Professor Donald R. Brown