Worcester Polytechnic Institute Electronic Theses and Dissertations Collection

Title page for ETD etd-082507-073448


Document Typethesis
Author NameCroughwell, Rosamaria
Email Address croughwell at comcast.net
URNetd-082507-073448
TitleA 16-b 10Msample/s Split-Interleaved Analog to Digital Converter
DegreeMS
DepartmentElectrical & Computer Engineering
Advisors
  • John McNeill, Advisor
  • Andrew Klein, Committee Member
  • Richard Vaz, Committee Member
  • Keywords
  • A/D Converter
  • Interleaved ADC
  • ADC
  • split-ADC
  • Analog-to-Digital Converter
  • Date of Presentation/Defense2007-08-24
    Availability unrestricted

    Abstract

    This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels.

    The ‘split ADC’ is a new concept that allows the use of a deterministic, digital, self calibrating algorithm. In this approach, an ADC is split into two paths, producing two output codes from the same input sample. The difference of these two codes is used as the calibration signal for an LMS error estimation algorithm that drives the difference error to zero. The ADC is calibrated when the codes are equal and the output is taken as the average of the two codes.

    The ‘split’ ADC concept and interleaved architecture are combined in this IC design to form the core of a high speed, high resolution, and self-calibrating ADC system. The dual outputs are used to drive a digital calibration engine to correct for the channel mismatch errors. This system has the speed benefits of interleaving while maintaining high resolution. The hardware for the algorithm as well as the ADC can be implemented in a standard 0.25um CMOS process, resulting in a relatively inexpensive solution. This work is supported by grants from Analog Devices Incorporated (ADI) and the National Science Foundation (NSF).

    Files
  • croughwell.pdf

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